I'm looking into a 386SX upgrade for my 286 build.
The Intel 386 Hardware Reference Manual includes the following schematic for generating S0# and S1#.
The Hardware Reference Manual also states: The 80287 Processor Extension Acknowledge (PEACK#) input is pulled high. In an 80286 system, the 80286 generates PEACK# to disable the PEREQ output of the 80287 so that extra data is not transferred. Because the 80386 knows the length of the operand and will not transfer extra data, PEACK# is not needed or used in 80386 systems.
Given the above, I have updated my schematic as follows. I have added a PLD to manage the S0# and S1# generation.
Here is the logic I plan to use in the PLD. I started with the logic from the Hardware Reference Manual and removed the CS and WS inputs (I don't think I need them for my setup).
Updated PCB
Néstor pointed me to a nice reference from VLSI Technology Inc. I found this very helpful. Based on this, I took a stab at converting the PALASM to CUPL and compiled a JED file for my GAL (wow, that's a lot of acronyms).
Note: The CUPL code in the image above has been updated. For the latest version, see my GitHub (link at bottom of post).
I updated the schematic for my interposer.
As part of the PCB update, I switched from 4-layer to 2-layer. This will give me more flexibility in trace cutting and bodge wiring, if needed. I also made a version with 74573's for address latching.
YouTube user pvc suggested the CPU may have a minimum speed to operate correctly. As I reviewed the datasheet, the Am386SXL and Am386SXLV support fully static operation. However, the processor I am using is the Am386SX, which lists 2 MHz as the lowest supported CPU clock. And... my debugger will not likely support this kind of speed. So, two things I now have on my list -- debugging with an Am386SXL and upgrading the debugger. I have ordered a few of the SXL processors so that I can run at slow speeds. As far as the debugger, I think I will swap out the Arduino Mega with an STM32 Nucleo-144 development board with STM32H723ZG MCU; this should give me faster processing capabilities and faster transfer speeds to the PC. As I read the specs on the STM32H723ZG, it appears that some of the pins are 5V tolerant, which will be helpful. Maybe in a future version of the debugger PCB, I will add an ISA edge connector (so that I can plug it directly into an ISA slot) and add voltage level shifters onboard.
Running!
I now have the 386SX upgrade running in my 286 build.
I have posted the EasyEDA source project for the 386SX upgrade interposer, Gerber files, and GAL files (.PLD source & .JED image). See x86/286-related/386SX-Upgrade-Interposer at main · rehsd/x86 (github.com).
The thing I most look forward to with a 386SX... two more segment registers!!
Resources
231732-001_80386_Hardware_Reference_Manual_1986.pdf (bitsavers.org)
VTI_ComputerProducts_1989_text.pdf, Section 7. Thank you Néstor for the pointer to this!
Great job!
You can avoid going from PALASM to CUPL by using GALASM.