As a continuation of FPGA VHDL Implementation of Ben Eater's 8-bit CPU - Progress Update, here's another update on my 8-bit CPU in VHDL project.
I have the core functionality working!
I can now add two numbers. I know... don't get too excited. :) But honestly, I'm pretty stoked to have gotten this all working. Here's a quick video showing my current FPGA implementation of Ben's 8-bit CPU (up through his CPU reset video).
While the code I have built so far is quite rough and will need some improvement, what I used in the video can be accessed on my GitHub; I added a new FPGA repository.
Next Steps
I plan to add the rest of the CPU instructions used in Ben's videos (e.g., subtract and jump). I also plan to clean up the code (e.g., consistency in formatting, code commenting, and performance improvement). If I get energetic, I might re-open a Windows interface I wrote for my breadboard 8-bit CPU and see if I can make it work with this FPGA solution; uploading RAM values would be handy.
As a reminder, I am very new to FPGA solution development. If you have suggestions on how to improve what I have built so far, please let me know!
Postscript
Here are some images of the FPGA implementation. Crazy...
PPS
I have added support for CPU instructions SUB, STA, LDI, and JMP. The following video demonstrates Ben's "add 3 and JMP" program from Adding more machine language instructions to the CPU.
Here is the current block design:
Code has been posted here. Next: implement JC and JZ instructions.
PPPS
I added support for the final instructions from Ben's video series: JC and JZ conditional jumps. The following video shows a program from Ben's Conditional jump instructions video.
Code has been posted here.
**In the last video, the flag bits were not being displayed correctly on the OLED display (but were being processed correctly). This has been fixed.